This invention relates generally to flash-type analog-to-digital converters and more particularly to a flash-type analog-to-digital converter employing a high speed decoding apparatus.
As is well known, flash-type analog-to-digital (A/D) converters also referred to as parallel converters are widely employed to develop ultra-fast conversions which are of the type for example required in video signal processing, in radar applications and other applications as well. In regard to such techniques up to 8 bits resolution is normally required, and in order to accommodate ultra-fast conversions with such resolution, the prior art has employed parallel or flash converters.
Flash or parallel type A/D converters or, as they are sometimes called, simultaneous A/D converters offer high speed of operation and are probably the highest speed type of converter available. Such converters use an analog comparator for every quantization level in the coded digital word. Since the conversion is performed in one step, rates of 100 megabits per second or greater can be achieved. However, because the amount of equipment needed is practically doubled for each additional binary bit of resolution, parallel converters are usually employed where the requirement is for low resolution, that is, high speed 3-to 8-bit conversions systems.
A limitation of the method in parallel converters is the large number of comparators required for even moderate resolutions. For example, a 4-bit converter requires only 15 comparators, but an 8 bit converter needs 255. Hence, the prior art has employed many techniques in order to improve operation of such parallel converters. For examples of typical devices, reference is made to a text entitled Analog-to-Digital /Digital-to-Analog Conversion Techniques by David F. Hoeschele, Jr., published by John Wiley & Sons, Inc. 1968. See Chapter 12 entitled "Analog-to-Digital Converter Design", pages 366 to 429. There are of course many other examples of flash analog-to-digital converters in the prior art.
In a flash analog-to-digital converter whether it be fabricated by CMOS technology or otherwise an error code condition can occur at a specific sampling frequency and input bandwidth which is commonly known as a "sparkle". The term "sparkle" is derived from the fact that such converters may be employed in television systems and when two codes are simultaneously decoded a pixel appears as a bright spot due to the error and appears as a "sparkle" on the television display. A "sparkle" occurs when two codes are simultaneously decoded; thus a "sparkle" could occur based on the following. For example, a first code could be indicative of 0111 1111 (127). A second code would be 1000 0000 (128). The combination of codes 1 and 2 would yield all ones or 1111 1111 (255). The error results in a decimal decode of 255 instead of 127 or 128 and this is an extremely large error indicative of a "sparkle". The "sparkle" can occur under two conditions. The first condition is at a high sampling rate and there will always be a sampling frequency where the decoder is simply not fast enough to decode the correct count.
A second condition is where one is operating with a high slew rate input signal. If the input signal has a high slew rate condition then the comparators and the decoder might not be able to track the input. The prior art as will be subsequently explained, proposed various solutions to solve the "sparkle" problem. One prior art solution employed double latched comparators in order to circumvent the "sparkle" problem. However this scheme requires two latches and introduces additional delay.
It is therefore an object of the present invention to provide apparatus which operates in conjunction with a flash analog-to-digital converter and which apparatus serves to circumvent the above-noted "sparkle" problem while further providing high-speed decoding.